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EvTensorAbi.h File

Mirrored EV-side tensor ABI used to communicate with EV74 kernels. More...

Included Headers​

#include <stdint.h>

Classes Index​

structsima_ev_abi_header

Common header at the start of every per-op config block. More...

structsima_ev_storage_desc

Device-visible storage backing a tensor descriptor. More...

structsima_ev_strided_desc

Logical strided tensor view (rank + sizes + byte strides). More...

structsima_ev_tiled_desc

Physical tiled tensor view. More...

structsima_ev_quant_desc

Optional quantization metadata. More...

structsima_ev_tensor_desc

Full per-tensor descriptor: dtype, layout, storage, optional quant. More...

structsima_ev_tess_config_v1

Tess (tessellate) op config: 1 input, 1 output. More...

structsima_ev_detess_config_v1

Detess (detessellate) op config: 1 input, 1 output. More...

structsima_ev_quantize_config_v1

Quantize op config: 1 input, 1 output, plus rounding/saturation modes. More...

structsima_ev_dequantize_config_v1

Dequantize op config: 1 input, 1 output. More...

structsima_ev_tensor_list_v1

Multi-tensor IO shell used by kernels like detessdequant. More...

structsima_ev_detessdequant_params_v1

Per-output detessdequant parameters. More...

structsima_ev_detessdequant_config_v1

DetessDequant op config: many inputs, many outputs, per-output params. More...

structsima_ev_roi_v1

Region-of-interest rectangle, in pixels. More...

structsima_ev_preproc_config_v1

Preproc op config: 1 input image, 1 output tensor, plus crop/resize/normalize. More...

Enumerations Index​

anonymous enum { ... }

ABI-wide capacity constants and version identifier. More...

enumsima_ev_op_type { ... }

Operation-type tag carried in sima_ev_abi_header::op_type. More...

enumsima_ev_addr_space { ... }

Address-space selector for sima_ev_storage_desc::addr. More...

enumsima_ev_dtype { ... }

Element types the ABI can describe. More...

enumsima_ev_layout_kind { ... }

Layout family carried in sima_ev_tensor_desc::logical_kind/physical_kind. More...

enumsima_ev_axis_semantic { ... }

Optional per-axis semantic tag (advisory metadata). More...

enumsima_ev_quant_scheme { ... }

Quantization scheme tag for sima_ev_quant_desc::scheme. More...

enumsima_ev_round_mode { ... }

Rounding mode used by quantize/cast kernels. More...

Description​

Mirrored EV-side tensor ABI used to communicate with EV74 kernels.

This header captures a candidate common ABI for EV kernels so host and firmware can converge on a single tensor/storage contract instead of per-graph ad hoc structs. It is currently a draft proposal — not yet wired into the live EV runtime — but it documents the shape of the per-op config blocks (tess, detess, quantize/dequantize, detessdequant, preproc) and the shared tensor/storage descriptor types they all reference.

The header is C-callable so firmware-side code can include it directly. All values are POD; layout is fixed by the structs themselves.

Enumerations​

anonymous enum​

anonymous enum

ABI-wide capacity constants and version identifier.

Enumeration values
SIMA_EV_ABI_VERSION_1Current ABI version tag (carried in sima_ev_abi_header) (= 1)
SIMA_EV_MAX_RANKMaximum tensor rank supported by descriptors (= 8)
SIMA_EV_MAX_IOMaximum number of inputs/outputs per multi-IO kernel (= 32)

Definition at line 34 of file EvTensorAbi.h.

34enum {
35 SIMA_EV_ABI_VERSION_1 = 1,
36 SIMA_EV_MAX_RANK = 8,
37 SIMA_EV_MAX_IO = 32,
38};

sima_ev_addr_space​

enum sima_ev_addr_space

Address-space selector for sima_ev_storage_desc::addr.

Enumeration values
SIMA_EV_ADDR_BUSBus address (canonical long-term) (= 0)
SIMA_EV_ADDR_PHYSPhysical address (transitional) (= 1)

Definition at line 54 of file EvTensorAbi.h.

54enum sima_ev_addr_space {
55 SIMA_EV_ADDR_BUS = 0,
56 SIMA_EV_ADDR_PHYS = 1,
57};

sima_ev_axis_semantic​

enum sima_ev_axis_semantic

Optional per-axis semantic tag (advisory metadata).

Enumeration values
SIMA_EV_AXIS_UNKNOWN (= 0)
SIMA_EV_AXIS_NBatch (= 1)
SIMA_EV_AXIS_CChannel (= 2)
SIMA_EV_AXIS_DDepth (= 3)
SIMA_EV_AXIS_HHeight (= 4)
SIMA_EV_AXIS_WWidth (= 5)

Definition at line 81 of file EvTensorAbi.h.

81enum sima_ev_axis_semantic {
82 SIMA_EV_AXIS_UNKNOWN = 0,
83 SIMA_EV_AXIS_N = 1,
84 SIMA_EV_AXIS_C = 2,
85 SIMA_EV_AXIS_D = 3,
86 SIMA_EV_AXIS_H = 4,
87 SIMA_EV_AXIS_W = 5,
88};

sima_ev_dtype​

enum sima_ev_dtype

Element types the ABI can describe.

Enumeration values
SIMA_EV_DTYPE_INVALID (= 0)
SIMA_EV_DTYPE_INT8 (= 1)
SIMA_EV_DTYPE_INT16 (= 2)
SIMA_EV_DTYPE_INT32 (= 3)
SIMA_EV_DTYPE_BF16 (= 4)
SIMA_EV_DTYPE_FP16 (= 5)
SIMA_EV_DTYPE_FP32 (= 6)
SIMA_EV_DTYPE_UINT8 (= 7)
SIMA_EV_DTYPE_UINT16 (= 8)
SIMA_EV_DTYPE_UINT32 (= 9)

Definition at line 60 of file EvTensorAbi.h.

60enum sima_ev_dtype {
61 SIMA_EV_DTYPE_INVALID = 0,
62 SIMA_EV_DTYPE_INT8 = 1,
63 SIMA_EV_DTYPE_INT16 = 2,
64 SIMA_EV_DTYPE_INT32 = 3,
65 SIMA_EV_DTYPE_BF16 = 4,
66 SIMA_EV_DTYPE_FP16 = 5,
67 SIMA_EV_DTYPE_FP32 = 6,
68 SIMA_EV_DTYPE_UINT8 = 7,
69 SIMA_EV_DTYPE_UINT16 = 8,
70 SIMA_EV_DTYPE_UINT32 = 9,
71};

sima_ev_layout_kind​

enum sima_ev_layout_kind

Layout family carried in sima_ev_tensor_desc::logical_kind/physical_kind.

Enumeration values
SIMA_EV_LAYOUT_STRIDEDStandard rank/sizes/strides view (= 0)
SIMA_EV_LAYOUT_TILEDTiled view with explicit tile geometry (= 1)
SIMA_EV_LAYOUT_OPAQUEOpaque blob (kernel-private layout) (= 2)

Definition at line 74 of file EvTensorAbi.h.

74enum sima_ev_layout_kind {
75 SIMA_EV_LAYOUT_STRIDED = 0,
76 SIMA_EV_LAYOUT_TILED = 1,
77 SIMA_EV_LAYOUT_OPAQUE = 2,
78};

sima_ev_op_type​

enum sima_ev_op_type

Operation-type tag carried in sima_ev_abi_header::op_type.

Enumeration values
SIMA_EV_OP_INVALIDInvalid/unset (= 0)
SIMA_EV_OP_TESSTessellate (= 1)
SIMA_EV_OP_DETESSDetessellate (= 2)
SIMA_EV_OP_QUANTIZEQuantize (= 3)
SIMA_EV_OP_DEQUANTIZEDequantize (= 4)
SIMA_EV_OP_QUANTTESSFused quantize + tessellate (= 5)
SIMA_EV_OP_DETESSDEQUANTFused detessellate + dequantize (= 6)
SIMA_EV_OP_PREPROCImage preprocessing (= 7)
SIMA_EV_OP_CASTElement-type cast (e.g., BF16 ↔ FP32) (= 8)

Definition at line 41 of file EvTensorAbi.h.

41enum sima_ev_op_type {
42 SIMA_EV_OP_INVALID = 0,
43 SIMA_EV_OP_TESS = 1,
44 SIMA_EV_OP_DETESS = 2,
45 SIMA_EV_OP_QUANTIZE = 3,
46 SIMA_EV_OP_DEQUANTIZE = 4,
47 SIMA_EV_OP_QUANTTESS = 5,
48 SIMA_EV_OP_DETESSDEQUANT = 6,
49 SIMA_EV_OP_PREPROC = 7,
50 SIMA_EV_OP_CAST = 8,
51};

sima_ev_quant_scheme​

enum sima_ev_quant_scheme

Quantization scheme tag for sima_ev_quant_desc::scheme.

Enumeration values
SIMA_EV_QUANT_NONENo quantization (other fields zeroed) (= 0)
SIMA_EV_QUANT_PER_TENSOR_AFFINESingle (scale, zero-point) for the whole tensor (= 1)
SIMA_EV_QUANT_PER_AXIS_AFFINEPer-axis (scale, zero-point) arrays (= 2)

Definition at line 91 of file EvTensorAbi.h.

91enum sima_ev_quant_scheme {
92 SIMA_EV_QUANT_NONE = 0,
93 SIMA_EV_QUANT_PER_TENSOR_AFFINE = 1,
94 SIMA_EV_QUANT_PER_AXIS_AFFINE = 2,
95};

sima_ev_round_mode​

enum sima_ev_round_mode

Rounding mode used by quantize/cast kernels.

Enumeration values
SIMA_EV_ROUND_DEFAULT (= 0)
SIMA_EV_ROUND_TO_ZERO (= 1)
SIMA_EV_ROUND_TO_EVEN (= 2)
SIMA_EV_ROUND_TO_POS_INF (= 3)
SIMA_EV_ROUND_TO_NEG_INF (= 4)

Definition at line 98 of file EvTensorAbi.h.

98enum sima_ev_round_mode {
99 SIMA_EV_ROUND_DEFAULT = 0,
100 SIMA_EV_ROUND_TO_ZERO = 1,
101 SIMA_EV_ROUND_TO_EVEN = 2,
102 SIMA_EV_ROUND_TO_POS_INF = 3,
103 SIMA_EV_ROUND_TO_NEG_INF = 4,
104};

File Listing​

The file content with the documentation metadata removed is:

1
16#pragma once
17
18#ifdef __cplusplus
19#include <cstdint>
20extern "C" {
21#else
22#include <stdint.h>
23#endif
24
25/*
26 * Draft proposal only.
27 *
28 * This header is not wired into the live EV runtime yet. It captures a
29 * candidate common ABI for EV kernels so host and firmware can converge on one
30 * tensor/storage contract instead of per-graph ad hoc structs.
31 */
32
34enum {
35 SIMA_EV_ABI_VERSION_1 = 1,
36 SIMA_EV_MAX_RANK = 8,
37 SIMA_EV_MAX_IO = 32,
38};
39
41enum sima_ev_op_type {
42 SIMA_EV_OP_INVALID = 0,
43 SIMA_EV_OP_TESS = 1,
44 SIMA_EV_OP_DETESS = 2,
45 SIMA_EV_OP_QUANTIZE = 3,
46 SIMA_EV_OP_DEQUANTIZE = 4,
47 SIMA_EV_OP_QUANTTESS = 5,
48 SIMA_EV_OP_DETESSDEQUANT = 6,
49 SIMA_EV_OP_PREPROC = 7,
50 SIMA_EV_OP_CAST = 8,
51};
52
54enum sima_ev_addr_space {
55 SIMA_EV_ADDR_BUS = 0,
56 SIMA_EV_ADDR_PHYS = 1,
57};
58
60enum sima_ev_dtype {
61 SIMA_EV_DTYPE_INVALID = 0,
62 SIMA_EV_DTYPE_INT8 = 1,
63 SIMA_EV_DTYPE_INT16 = 2,
64 SIMA_EV_DTYPE_INT32 = 3,
65 SIMA_EV_DTYPE_BF16 = 4,
66 SIMA_EV_DTYPE_FP16 = 5,
67 SIMA_EV_DTYPE_FP32 = 6,
68 SIMA_EV_DTYPE_UINT8 = 7,
69 SIMA_EV_DTYPE_UINT16 = 8,
70 SIMA_EV_DTYPE_UINT32 = 9,
71};
72
74enum sima_ev_layout_kind {
75 SIMA_EV_LAYOUT_STRIDED = 0,
76 SIMA_EV_LAYOUT_TILED = 1,
77 SIMA_EV_LAYOUT_OPAQUE = 2,
78};
79
81enum sima_ev_axis_semantic {
82 SIMA_EV_AXIS_UNKNOWN = 0,
83 SIMA_EV_AXIS_N = 1,
84 SIMA_EV_AXIS_C = 2,
85 SIMA_EV_AXIS_D = 3,
86 SIMA_EV_AXIS_H = 4,
87 SIMA_EV_AXIS_W = 5,
88};
89
91enum sima_ev_quant_scheme {
92 SIMA_EV_QUANT_NONE = 0,
93 SIMA_EV_QUANT_PER_TENSOR_AFFINE = 1,
94 SIMA_EV_QUANT_PER_AXIS_AFFINE = 2,
95};
96
98enum sima_ev_round_mode {
99 SIMA_EV_ROUND_DEFAULT = 0,
100 SIMA_EV_ROUND_TO_ZERO = 1,
101 SIMA_EV_ROUND_TO_EVEN = 2,
102 SIMA_EV_ROUND_TO_POS_INF = 3,
103 SIMA_EV_ROUND_TO_NEG_INF = 4,
104};
105
112struct sima_ev_abi_header {
113 uint16_t abi_version;
114 uint16_t op_type;
115 uint32_t flags;
116 uint32_t num_inputs;
117 uint32_t num_outputs;
118 uint32_t reserved[2];
119};
120
121/*
122 * Device-visible storage. For long-term consistency, BUS should be the
123 * canonical address space, but the field remains explicit during migration.
124 */
132struct sima_ev_storage_desc {
133 uint64_t addr;
134 uint64_t nbytes;
135 uint32_t addr_space;
136 uint32_t alignment_bytes;
137 int64_t storage_offset_bytes;
138 uint64_t reserved0;
139};
140
141/*
142 * Logical tensor view, intentionally close to PyTorch semantics: rank, sizes,
143 * and byte strides are authoritative. Axis semantics are advisory metadata for
144 * validation, debugging, and kernels that want explicit N/C/D/H/W naming.
145 */
153struct sima_ev_strided_desc {
154 uint32_t rank;
155 uint8_t axis_semantics[SIMA_EV_MAX_RANK];
156 uint8_t reserved0[4];
157 int64_t sizes[SIMA_EV_MAX_RANK];
158 int64_t strides_bytes[SIMA_EV_MAX_RANK];
159};
160
161/*
162 * Physical tiled view. This is separate from the logical view because a tiled
163 * EV buffer is not just a dense tensor with different strides: it also has tile
164 * shape, tile traversal order, inner blocking, and per-tile alignment rules.
165 */
173struct sima_ev_tiled_desc {
174 uint32_t rank;
175 uint8_t axis_semantics[SIMA_EV_MAX_RANK];
176 uint8_t tile_axis_order[SIMA_EV_MAX_RANK];
177 uint8_t inner_block[SIMA_EV_MAX_RANK];
178 uint8_t reserved0[4];
179 int64_t tile_sizes[SIMA_EV_MAX_RANK];
180 uint32_t tile_align_bytes;
181 uint32_t flags;
182};
183
184/*
185 * Optional quantization metadata. Kernels that do not use quantization should
186 * set scheme=SIMA_EV_QUANT_NONE and leave the remaining fields zeroed.
187 */
195struct sima_ev_quant_desc {
196 uint32_t scheme;
197 uint32_t quant_axis;
198 float scale;
199 int32_t zero_point;
200 uint64_t scale_addr;
201 uint64_t zero_point_addr;
202 uint32_t param_count;
203 uint32_t reserved0;
204};
205
213struct sima_ev_tensor_desc {
214 uint32_t dtype;
215 uint32_t logical_kind;
216 uint32_t physical_kind;
217 uint32_t flags;
218 struct sima_ev_storage_desc storage;
219 struct sima_ev_strided_desc logical;
220 union {
221 struct sima_ev_strided_desc strided;
222 struct sima_ev_tiled_desc tiled;
223 } physical;
224 struct sima_ev_quant_desc quant;
225};
226
227/*
228 * Single-input/single-output transforms.
229 */
231struct sima_ev_tess_config_v1 {
232 struct sima_ev_abi_header hdr;
233 struct sima_ev_tensor_desc input;
234 struct sima_ev_tensor_desc output;
235};
236
238struct sima_ev_detess_config_v1 {
239 struct sima_ev_abi_header hdr;
240 struct sima_ev_tensor_desc input;
241 struct sima_ev_tensor_desc output;
242};
243
245struct sima_ev_quantize_config_v1 {
246 struct sima_ev_abi_header hdr;
247 struct sima_ev_tensor_desc input;
248 struct sima_ev_tensor_desc output;
249 uint32_t round_mode;
250 uint32_t saturate_mode;
251 uint32_t reserved[2];
252};
253
255struct sima_ev_dequantize_config_v1 {
256 struct sima_ev_abi_header hdr;
257 struct sima_ev_tensor_desc input;
258 struct sima_ev_tensor_desc output;
259 uint32_t reserved[4];
260};
261
262/*
263 * Shared multi-IO shell for kernels such as detessdequant that naturally operate
264 * on many heads/tensors per dispatch.
265 */
271struct sima_ev_tensor_list_v1 {
272 uint32_t count;
273 uint32_t reserved[3];
274 struct sima_ev_tensor_desc desc[SIMA_EV_MAX_IO];
275};
276
278struct sima_ev_detessdequant_params_v1 {
279 uint32_t fp16_output;
280 uint32_t round_mode;
281 uint32_t reserved[2];
282};
283
285struct sima_ev_detessdequant_config_v1 {
286 struct sima_ev_abi_header hdr;
287 struct sima_ev_tensor_list_v1 inputs;
288 struct sima_ev_tensor_list_v1 outputs;
289 struct sima_ev_detessdequant_params_v1 params[SIMA_EV_MAX_IO];
290};
291
292/*
293 * Example preproc payload. Preproc is intentionally kept as a small per-op
294 * wrapper over the shared tensor descriptors rather than forcing all kernels
295 * into a single giant transform struct.
296 */
298struct sima_ev_roi_v1 {
299 int32_t x;
300 int32_t y;
301 int32_t width;
302 int32_t height;
303};
304
312struct sima_ev_preproc_config_v1 {
313 struct sima_ev_abi_header hdr;
314 struct sima_ev_tensor_desc input;
315 struct sima_ev_tensor_desc output;
316 struct sima_ev_roi_v1 crop;
317 int32_t resize_width;
318 int32_t resize_height;
319 uint32_t color_in;
320 uint32_t color_out;
321 float normalize_scale[4];
322 float normalize_bias[4];
323};
324
325#ifdef __cplusplus
326} /* extern "C" */
327#endif

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