Tensor

Tensor core types, constraints, conversions, adapters. More...

Classes Index

struct	ConversionTrace
	Single audit-log entry for a conversion that occurred. More...
struct	ImageSpec
	Image-tensor metadata: pixel format and (optional) color space. More...
struct	EncodedSpec
	Encoded-stream tensor metadata: which codec the bytes represent. More...
struct	ByteStreamSpec
	Opaque byte-stream tensor metadata. More...
struct	QuantSpec
	Quantization metadata for INT8/INT16 tensors. More...
struct	TessSpec
	Tessellation metadata — tile geometry for the MLA's tile-block layout. More...
struct	PreprocessRuntimeMeta
	Per-buffer preprocessing context — the inverse-transform breadcrumb trail. More...
struct	Semantic
	Discriminated union of "what this tensor represents". More...
struct	Mapping
	Scoped read/write window into a TensorBuffer. More...
struct	TensorBuffer
	Storage handle for a tensor — opaque container for one of four backing memory kinds. More...
struct	Plane
	One plane of a composite (multi-plane) tensor. More...
struct	TensorRouteMeta
	Routing metadata that travels with a tensor through multi-output pipelines. More...
struct	Tensor
	Universal tensor type — a labeled box of numbers that flows between Nodes. More...
struct	TensorConstraint
	Declarative tensor contract — describes the shape/dtype/device/format a tensor must satisfy. More...

Typedefs Index

using	ByteFormat = ByteStreamSpec::ByteFormat
	Convenience top-level alias for ByteStreamSpec::ByteFormat. More...

Enumerations Index

enum class	ConversionKind { ... }
	What kind of transformation a tensor conversion represents. More...
enum class	ConversionPolicy { ... }
	How strict the framework is about implicit tensor conversions. More...
enum class	DeviceType { ... }
	Where a tensor's data lives — which processor can read it directly. More...
enum class	StorageKind { ... }
	How a TensorBuffer's memory was acquired and how to access it. More...
enum class	PlaneRole { ... }
	Role of a plane within a composite (multi-plane) tensor. More...
enum class	TensorDType { ... }
	Element data type of a tensor. More...
enum class	TensorAxisSemantic : uint8_t { ... }
	Per-axis semantic tag — the long-term layout vocabulary. More...
enum class	TensorLayout { ... }
	Transition-only coarse layout token (HWC / CHW / HW). More...

Description

Tensor core types, constraints, conversions, adapters.

Typedefs

ByteFormat

using simaai::neat::ByteFormat = typedef ByteStreamSpec::ByteFormat

Convenience top-level alias for ByteStreamSpec::ByteFormat.

Definition at line 216 of file TensorCore.h.

216using ByteFormat = ByteStreamSpec::ByteFormat;

Enumerations

ConversionKind

enum class simaai::neat::ConversionKind

strong

What kind of transformation a tensor conversion represents.

Enumeration values

Reinterpret	Same bytes, different dtype/layout label. No memory traffic (= 0)
View	Pointer-arithmetic view (sub-tensor or strided slice). No copy
Pack	Byte-level rearrangement in place (e.g., layout swap, packing)
Convert	Element-wise math conversion (e.g., FP32 → BF16, INT8 → FP32)
Transfer	Cross-device transfer (e.g., CPU → accelerator scratch memory)

Ordered roughly cheapest-to-most-expensive: a Reinterpret is free (just a type/dtype relabel), a View is free (sub-tensor pointer arithmetic), a Pack rearranges bytes in-place, a Convert does math (e.g., FP32 → BF16), and a Transfer moves data across device boundaries (e.g., CPU → MLA scratchpad).

Definition at line 31 of file TensorConversion.h.

31enum class ConversionKind {

32 Reinterpret = 0,

33 View,

34 Pack,

35 Convert,

36 Transfer,

37};

ConversionPolicy

enum class simaai::neat::ConversionPolicy

strong

How strict the framework is about implicit tensor conversions.

Enumeration values

Strict	Refuse implicit conversions; require explicit user code (= 0)
AllowWithTrace	Allow but record each conversion to a trace collector
AllowSilent	Allow without tracking

Strict (default for many internal validations) refuses any implicit conversion; AllowWithTrace permits the conversion but records it to a ConversionTraceCollector for later auditing; AllowSilent permits without recording.

Definition at line 47 of file TensorConversion.h.

47enum class ConversionPolicy {

48 Strict = 0,

49 AllowWithTrace,

50 AllowSilent,

51};

DeviceType

enum class simaai::neat::DeviceType

strong

Where a tensor's data lives — which processor can read it directly.

Enumeration values

CPU	Host A65 (general-purpose CPU) (= 0)
SIMA_APU	Audio Processing Unit
SIMA_CVU	Compute/Vector Unit (EV74)
SIMA_MLA	Machine Learning Accelerator
UNKNOWN	Placement not specified

The Modalix's heterogeneous compute is reflected here. CPU is the host A65; SIMA_CVU is the EV74 vector processor's accessible memory; SIMA_MLA is the ML accelerator's scratchpad; SIMA_APU is the audio processing unit. Tensors with the same buffer can sometimes be accessed from multiple devices (zero-copy via unified IOMMU); other times an explicit transfer is required.

Definition at line 57 of file TensorCore.h.

57enum class DeviceType {

58 CPU = 0,

59 SIMA_APU,

60 SIMA_CVU,

61 SIMA_MLA,

62 UNKNOWN,

63};

PlaneRole

enum class simaai::neat::PlaneRole

strong

Role of a plane within a composite (multi-plane) tensor.

Enumeration values

Unknown	(= 0)
Y	Luminance plane
U	Chrominance-U plane (I420)
V	Chrominance-V plane (I420)
UV	Interleaved chrominance plane (NV12)

Composite tensors carry their planes as separate Plane records. NV12 has Y + UV; I420 has Y + U + V; single-plane formats use the default Unknown.

Definition at line 112 of file TensorCore.h.

112enum class PlaneRole {

113 Unknown = 0,

114 Y,

115 U,

116 V,

117 UV,

118};

StorageKind

enum class simaai::neat::StorageKind

strong

How a TensorBuffer's memory was acquired and how to access it.

Enumeration values

CpuOwned	Framework allocated; freed when the storage refcount hits zero (= 0)
CpuExternal	Wraps a foreign pointer; lifetime tracked via holder
GstSample	References a GStreamer pool sample; refcounted via GStreamer
DeviceHandle	Lives in accelerator memory; CPU access requires an explicit transfer
Unknown

Determines the framework's strategy for map() and lifetime management. CpuOwned is the default — framework allocated, framework frees. CpuExternal wraps a foreign pointer (cv::Mat data, NumPy array, mmap'd file). GstSample carries a reference to a GStreamer buffer pool sample. DeviceHandle lives in accelerator memory (e.g., MLA scratchpad) and requires an explicit transfer for CPU access.

Definition at line 81 of file TensorCore.h.

81enum class StorageKind {

82 CpuOwned = 0,

83 CpuExternal,

84 GstSample,

85 DeviceHandle,

86 Unknown,

87};

TensorAxisSemantic

enum class simaai::neat::TensorAxisSemantic : uint8_t

strong

Per-axis semantic tag — the long-term layout vocabulary.

Enumeration values

Unknown	Axis role not annotated (= 0)
N	Batch axis
D	Depth axis (5D tensors: batch + depth + spatial)
H	Height (spatial)
W	Width (spatial)
C	Channel axis

Each axis of a tensor is tagged with a role: batch (N), depth (D), height (H), width (W), or channel (C). Together with shape and strides, this is the authoritative description of tensor layout and supersedes the coarse TensorLayout token for generic 3D/4D/5D tensors.

Definition at line 103 of file TensorTypes.h.

103enum class TensorAxisSemantic : uint8_t {

104 Unknown = 0,

105 N,

106 D,

107 H,

108 W,

109 C,

110};

TensorDType

enum class simaai::neat::TensorDType

strong

Element data type of a tensor.

Enumeration values

UInt8	8-bit unsigned integer (typical pixel values)
Int8	8-bit signed integer (typical quantized weights/activations)
UInt16	16-bit unsigned integer
Int16	16-bit signed integer
Int32	32-bit signed integer
BFloat16	16-bit "brain float" (1 sign + 8 exponent + 7 mantissa bits) — MLA's FP path
Float32	IEEE 754 single-precision (the user-facing default)
Float64	IEEE 754 double-precision

Note: floating-point variants include BFloat16 (16-bit "brain float", same dynamic range as Float32), Float32, and Float64. Float16 (IEEE half) is intentionally omitted — the framework targets BF16 for the MLA's floating-point path; FP16 has no first-class path.

Definition at line 83 of file TensorTypes.h.

83enum class TensorDType {

84 UInt8,

85 Int8,

86 UInt16,

87 Int16,

88 Int32,

89 BFloat16,

90 Float32,

91 Float64,

92};

TensorLayout

enum class simaai::neat::TensorLayout

strong

Transition-only coarse layout token (HWC / CHW / HW).

Enumeration values

Unknown	(= 0)
HWC	Height × Width × Channels (image-natural layout)
CHW	Channels × Height × Width (PyTorch-natural layout)
HW	Height × Width (single-channel / grayscale)

This is not the long-term semantic truth for generic tensors. Internal tensor semantics should move toward shape + strides + explicit axis_semantics, with layout tokens remaining only at boundary/compatibility surfaces during the migration. Prefer TensorAxisSemantic for new code.

See Also

TensorAxisSemantic

Definition at line 122 of file TensorTypes.h.

122enum class TensorLayout {

123 Unknown = 0,

124 HWC,

125 CHW,

126 HW,

127};

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